Broadcom’s demonstration and a follow-up session explored the advantages of additional growing CPC, similar to lowered sign integrity penalties and prolonged attain, by channel modeling and simulations, Broadcom wrote in a weblog in regards to the DesignCon occasion.
“Experimental outcomes confirmed profitable implementation of CPC, demonstrating its potential to handle bandwidth and sign integrity challenges in information facilities, which is essential for AI functions,” Broadcom acknowledged.
Along with the demo, Broadcom and Samtec additionally authored a white paper on CPC that acknowledged: “Co-packaged connectivity (CPC) supplies the chance to omit loss and reflection penalties from the [printed circuit board (PCB)] and the package deal. When excessive pace I/O is cabled from the highest of the package deal superior PCB supplies will not be mandatory. Losses from package deal vertical paths and PCB routing could be transferred to the longer attain of cables,” the authors acknowledged.
“As extremely complicated methods are challenged to scale the variety of I/O and their attain, co- packaged connectivity presents alternative. As we method 224G-PAM4 [which uses optical techniques to support 224 Gigabits per second data rates per optical lane] and above, system loss and dominating noise sources necessitate the necessity to re-consider that which has been restricted at the back of the system architect’s thoughts for years: What if we hooked up to the package deal?”
At OFC, Samtec demonstrated its Si-FlyHD co-packaged cable assemblies and Samtec FlyoverOctal Small Type-factor Pluggable (OSFP) over the Samtec Eye Velocity Hyper Low Skew twinax copper cable. Flyover is Samtec’s proprietary method of addressing sign integrity and attain limitations of routing high-speed indicators by conventional printed circuit boards (PCBs).
“This analysis platform incorporates Broadcom’s industry-leading 200G SerDes know-how and Samtec’s co-packaged Flyover know-how. Si-Fly HD CPC gives the {industry}’s highest footprint density and sturdy interconnect which permits 102.4T (512 lanes at 200G) in a 95 x 95 mm chip substrate,” Samtec wrote.